Micro-electromechanical systems

ABSTRACT

A MEMS incorporating a sensing element and a JFET electrically connected to the sensing element is fabricated by the steps of: forming a first layer of electrically insulating barrier material on a surface of a substrate; patterning the first layer so as to expose a first region of the substrate; doping by ion implantation the first region of the substrate to form a well region of the JFET; forming a second layer of barrier material on the surface of both the first layer and the first region of the substrate; patterning the barrier material so as to expose a part of the first region of the substrate; doping by ion implantation the exposed part of the first region of the substrate to form source and drain contact areas of the JFET; patterning the barrier material so as to expose a second region of the substrate; and doping by ion implantation the second region of the substrate to form gate and substrate contact areas of the JFET in a single implantion step. The monolithic integration of the JFET with the MEMS enables the bond wires for interconnecting the sensing element and the associated sensing electronic circuitry to be provided only after the buffering stage of such circuitry. This means that the bond wires interconnecting the buffering stage and the remainder of the circuitry are connected to a low impedance node which is less sensitive to noise and parasitic capacitive loading. Thus greater detection accuracy can be achieved by virtue of the fact that the parasitic capacitances are reduced to a minimum.

This invention relates to micro-electromechanical systems (MEMS), and isconcerned more particularly, but not exclusively, with such systemsincorporating a sensing element and a junction field-effect transistor(JFET) electrically connected to a capacitive sensing element, and to amethod of fabricating such a system.

In this specification the term “micro-electromechanical systems (MEMS)”is used to encompass a wide range of micromechanical sensors andactuators including those described in the art by the terms“Microsystems technology (MST)”, “microrobotics” and “microengineereddevices”.

It is known to produce MEMS using micro-machining techniques. Forexample GB 2276976A discloses a particular method of production of sucha system in which a silicon wafer has cavities formed in its surface,and a second wafer is then bonded to the surface of the first waferprior to the second wafer being etched in a manner to release portionsof the second wafer which are above the cavities in the first wafer. Inthis way a suspended resonating actuator is formed which can be actuatedin response to mechanical movement and which can be sensed by a sensingelement to provide an electrical output signal indicative of suchmovement. One such MEMS is the accelerometer disclosed in U.S. Pat. No.5,576,250.

WO 95/08775 and WO 00/16041 also relate to features of fabrication ofsuch MEMS.

In MEMS the capacitances to be detected are often well below 1 pF andusually in the capacitance range of fF−nF. Thus the required detectionaccuracy may be extremely small, that is less than 10 aF. Thus it isextremely important that the signal-to-noise ratio in transforming thesensed signal to an electrical output signal is maximised so as toenable small signals to be detected. Furthermore, since the detectedsignal is typically at a high impedance node (i.e. small capacitance),the signal is highly sensitive to noise injection. The signal is alsotypically of such a low value that it may be significantly attenuatedand potentially dominated by parasitics and/or the input capacitance ofthe amplifier for amplifying the detected signal. A simplified schematicdiagram of a typical capacitative detection circuit is shown in FIG. 1where C_(sense) denotes the capacitance of the sensing element, 2denotes a voltage source, 4 denotes the detection amplifier,C_(feedback) denotes the feedback capacitance, C_(in) denotes the inputcapacitance and C_(p) denotes the parasitic capacitance. V_(out) denotesthe voltage of the electrical output signal.

Typically MEMS sensors are provided on stand-alone silicon chips andemploy hybrid integration to interface to the sensing electroniccircuitry, whether discrete electronic circuitry is used (e.g.pin-through-hole or surface-mount on a printed circuit board), orwhether one or more integrated circuits are used in a multi-chip module(CM). The connections between the sensing element and the circuitry isnormally by way of one or more wire bonds and possibly a significantlength of conductive track and bond pads and/or wires. Such wire bonds,tracks and bond pads act as parasitic capacitances loading the outputand attenuating the signal to be amplified. The sensing circuitry mayincorporate one or more junction field-effect transistors (JFET) in theamplifier input since JFET's have low current noise performance and lowbias currents. Alternatively direct chip attach (DCA) techniques, suchas the flip-chip solder bump technique, may be used to mount the MEMSchip directly on the readout application specific integrated circuit(ASIC) which serves to reduce the parasitics (capacitance, resistanceand inductance of which capacitance is the most significant for thisapplication) to some extent.

S. Amon et al, “Self-Aligned Gate JFETs for Smart MEMS—Modeling, Designand Fabrication”, Journal of Modeling and Simulation of Microsystems,Vol. 1, No. 2, pages 105-108, 1999 discloses the integration ofself-aligned gate (SAG) JFETs with MEMS devices (fabricated using ionimplantation in bulk silicon with a substrate contact to the back of thewafer and implanted resistors) and the advantages provided by virtue ofthe fact that no epitaxial step is required in the fabrication process.J. J. Bernstein and J. T. Borenstein, “A Micromachined Silicon CondenserMicrophone with On-Chip Amplifier”, Solid State Sensor and ActuatorWorkshop, Hilton Head, S.C., Jun. 2-6, 1996 discloses a monolithicsilicon microphone with an integrated JFET source follower where theJFETs were fabricated in bulk silicon using a combination of solidsource doping and ion implantation with polysilicon resistors.

It is an object of the invention to provide a MEMS and a method forfabricating such a MEMS which enables the parasitic capacitances to beminimised so as to provide an improvement in the minimum detectablesignal.

According to one aspect of the present invention there is provided amethod of fabricating a micro-electromechanical system (MEMS)incorporating a sensing element and a junction field-effect transistor(JFET) electrically connected to the sensing element, the methodcomprising the steps of:

-   -   (a) forming a first layer of electrically insulating barrier        material on a surface of a substrate;    -   (b) patterning the first layer so as to expose a first region of        the substrate;    -   (c) doping by ion implantation the first region of the substrate        to form a well region of the JFET;    -   (d) forming a second layer of barrier material on the surface of        both the first layer and the first region of the substrate;    -   (e) patterning the barrier material so as to expose a part of        the first region of the substrate;    -   (f) doping by ion implantation the exposed part of the first        region of the substrate to form source and drain contact areas        of the JFET;    -   (g) patterning the barrier material so as to expose a second        region of the substrate; and    -   (h) doping by ion implantation the second region of the        substrate to form gate and substrate contact areas of the JFET        in a single implantion step.

According to a second aspect of the present invention there is provideda micro-electromechanical system (MEMS) comprising a substrateincorporating a movable element and an electrical sensing elementproviding an electrical output signal indicative of displacement of themovable element, wherein a junction field-effect transistor (JFET) ismonolithically integrated on the substrate with the sensing element andis electrically connected to the sensing element so as to act as animpedance transformer rendering the output signal less sensitive toexternal effects (such as noise and parasitic or stray capacitiveloading), and wherein gate and substrate contact areas of the JFET areformed on the same side of the substrate by a single ion implantationstep.

According to a third aspect of the present invention there is provided amicro-electromechanical system (MEMS) comprising a substrateincorporating a sensing element and a junction field-effect transistor(JFET) electrically connected to the sensing element, the system beingformed by the method of the first aspect.

The monolithic integration of the JFET of the sensing electroniccircuitry with the MEMS enables the bond wires for interconnecting thesensing element and the associated sensing electronic circuitry to beprovided only after the buffering stage of such circuitry. This meansthat the bond wires interconnecting the buffering stage and theremainder of the circuitry are connected to a low impedance node whichis less sensitive to noise and parasitic capacitive loading. Thusgreater detection accuracy can be achieved by virtue of the fact thatthe parasitic capacitances are reduced to a minimum.

Although, in theory, CMOS and BiCMOS analogue and digital electroniccircuitry may be used for the sensing electronics of such MEMS, eitheras a stand-alone ASIC or fully integrated, it should be pointed out thatthere are a number of disadvantages associated with use of CMOS devicesin such application. Firstly CMOS processing techniques can normallyonly be applied to [100] silicon substrate. Also the fabrication ofCMOS, bipolar and BiCMOS devices is complex requiring many additionalmasking steps, and may limit mechanical materials selection andproperties, as well as requiring a larger chip area and cost.

By contrast, the use of an integrated JFET considerably simplifies thefabrication process (typically to a 4 or 5 mask process) and enableslarger geometry devices to be used which do not require sub-micronprocess capabilities (or features), thus rendering the device simplerand cheaper to produce.

It is particularly advantageous for the system to be formed using asilicon-on-insulator (SOI), silicon on-glass (SOG) orsilicon-on-sapphire (SOS) substrate in the fabrication process sincethis allows mesa (trench) isolation to be employed for electricalisolation of individual JFET and sensing elements.

This permits the substrate potential of each JFET to be independentlyset if required for optimal circuit performance and eases circuitformation. Such substrates typically have thinner device layers and thuspresent higher resistance for in-plane current flow than their bulkequivalents. A further minor advantage is thus that the level of leakagecurrent associated with each JFET through the silicon may be decreased.

The invention also provides a method of fabricating amicro-electromechanical system (MEMS), the method comprising the stepsof applying a layer of a first material on a surface of a substrate of asecond material, selectively patterning the first material so as to forma track extending between two areas of the surface, and deep etching thesecond material so as to form a trench between the two areas whilstleaving the patterned first material in place, the deep etching beingadapted to undercut the second material beneath the track so that thetrack forms a bridge or cantilever across the trench.

In order that the invention may be more fully understood, preferredembodiments of the invention will now be described, by way of example,with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a typical capacitative detection circuitof a MEMS;

FIGS. 2 a to 2 e are diagrams showing successive steps in a fabricationmethod in accordance with the invention;

FIGS. 3 and 4 are layout diagrams of embodiments of the JFET portion ofthe MEMS in accordance with the invention;

FIGS. 5 and 6 are circuit diagrams of two preferred embodiments of MEMSin accordance with the invention;

FIGS. 7 and 8 show the preferred layouts of the integrated circuits ofthe embodiments of FIGS. 5 and 6 respectively;

FIG. 9 is a cross-section through the layout of FIG. 7; and

FIG. 10 is a schematic diagram of a metal bridge interconnecting twosilicon mesas.

In order to fabricate the JFET in such a system, a simple, four-maskprocess may be used as described below with reference to FIGS. 2 a to 2e showing sections through a portion of a substrate during successivefabrication steps.

The fabrication process to be described uses an n-type silicon wafer(typically of resistivity of around 10-30 ohm-cm) as a substrate, and afield oxide layer of a nominal thickness in the range of 0.2-1.0 μm, andtypically about 0.35 μm, is grown by a wet oxidation process. A similarfabrication process may be used in accordance with the invention toproduce an n-channel device in a p-type silicon wafer, but such devicestend to exhibit poorer noise performance. Furthermore somewhat similarfabrication processes may be used in accordance with the inventionutilising dielectric layers other than the field oxide layer referred toabove, and using alternative processing techniques, including such asLPCVD (low pressure chemical vapour deposition), PECVD (plasma enhancedchemical vapour deposition), spin-on thin films, evaporation,sputtering, etc.

FIG. 2 a shows the effect of a first lithographic process step in whicha photoresist layer is initially applied on top of the field oxide layerand is then exposed to radiation through a mask prior to the exposed orunexposed areas of the photoresist being removed (depending on whetherpositive or negative tone photoresist is used) and a suitable etchantbeing applied to selectively etch those areas from which the photoresisthas been removed. Alternatively the required patterning can by achievedby electron beam lithography. FIG. 2 a shows the field oxide layer 2 onthe substrate 1, and a window 3 which has been etched in the layer 2 inthis manner. Doping of a region 4 of the substrate 1 is then effected byimplantation of a p-type dopant, such as boron, through the window 3. Ina further annealing step the dopant is driven in to form a small p-typewell 5 as shown in FIG. 2 b, and a well oxide layer 6 is grown above thep-type well 5. The thickness of the well oxide layer 6 is preferablyapproximately one half of the thickness of the thickened field oxidelayer 2 covering the remainder of the substrate 1. This step renders theuse of a separate substrate contact mask unnecessary, as will beapparent from the description of the following fabrication steps. If itis necessary for the p-type well 5 to be deepened after the well oxidelayer 6 has been grown (or deposited) to the required depth, a furtherannealing step may be carried out in an inert ambient atmosphere.

Prior art JFET fabrication processes typically employ a contact on theback face of the substrate and typically involve fabrication in bulksilicon substrates. This is often as part of a full CMOS or bipolarfabrication process. Stand-alone JFET fabrication processes areconsiderably more complex than the process described with reference toFIGS. 2 a to 2 e, typically employing more masking steps.

Furthermore, if it is necessary to reduce the substrate leakage currentfrom the edge of the JFET (such leakage being primarily by way of aparasitic bipolar transistor associated with the edge of the device), itis possible for a further step to be incorporated in the fabricationmethod in which a nitride spacer 7 is created around the edge of thewell, as shown in FIG. 2 b. This spacer 7 can be produced by depositinga nitride layer, typically of a thickness of about 0.3-1.0 μm, on top ofthe oxide layers 2 and 6, and then blanket etching the nitride layerusing an anisotropic etch process leaving the required spacer 7 at thewell edge. The skilled person will appreciate that this could also bedone with oxide if it is acceptable to sacrifice etch selectivity to thetop of the barrier layer (which is also of oxide). The spacer acts tolevel shift the turn-on voltage of the parasitic bipolar transistorabove the pinch-off voltage of the JFET.

In a second lithographic process step a layer of photoresist applied tothe upper surface of the substrate is selectively exposed through afurther mask, and the exposed or unexposed areas of photoresist areremoved prior to etching of the well oxide layer 6 to form contactwindows 8 and 9 for the source and drain of the JFET, as shown in FIG. 2c. At the same at least one etched recess 10 may be formed in thethickened oxide layer 2 by such an etching process. It is important thatthe recess 10 is separated from the substrate 1 by a remaining thicknessof oxide, typically amounting to approximately half the thickness of theunetched parts of the oxide layer 2. In a further doping step a p⁺-typedopant is implanted in the p-type well 5 through the windows 8 and 9 toform source and drain contact areas 11 and 12 within the substrate 1.The remaining oxide layer separating the recess 10 from the substrate 1needs to be sufficient to ensure that such doping does not reach thearea of the substrate below the recess 10.

In a third lithographic process step a layer of photoresist applied tothe upper surface is selectively exposed through a further mask and,after removal of the exposed or unexposed photoresist, contact windows14 and 15 are etched in the oxide layers 2 and 6, as shown in FIG. 2 d,the window 15 extending through the remaining oxide previouslyseparating the recess 10 from the substrate 1. In a further doping stepa n⁺-type dopant is implanted through the windows 14 and 15 to form gateand substrate contact areas 16 and 17 in the substrate 1. The source anddrain contact areas 11 and 12 are protected by the photoresist mask fromthe gate and substrate contact implant. At the end of each cycle, thephotoresist mask is removed. Such a mask could also be used to defineother implants (e.g. source and drain contacts or well) without the needfor the formation of an oxide layer.

Annealing of the wafer in dry oxygen serves to activate the dopants andto drive the gate contact area 16 to the required depth in the p-typewell 5. During this annealing step a relatively thin oxide layer isformed in the contact windows. The surface is then blanket etched toremove the relatively thin layer of oxide in the contact windows, and alayer of a suitable metal, such as an aluminium alloy, Ti, TiW alloy,Au, Cr, Cu, W, Ni, Cr, NiCr alloy, TiN (titanium nitride), Pt andcombinations thereof for example, is deposited.

Annealing and activation of the implanted dopants may alternatively beundertaken in an inert atmosphere such as argon or nitrogen. In suchcases there may not be a thin oxide grown on the surfaces of the exposedsilicon and therefore there may be no need to perform a blanket etchprior to depositing the metal layer.

In a fourth lithographic process step a layer of photoresist applied tothe metal layer is then selectively etched through a further mask todefine the required metallisation pattern, and, after removal of theexposed or unexposed photoresist, the metal is removed by etching in theareas in which it is not required leaving the metallisation tracks 18 inplace. The metallisation could alternatively be patterned by milling orby lift-off processing (involving application of pattern photoresistprior to metal deposition and lift-off).

The above-described fabrication scheme is particularly advantageous asit requires the use of only four different masks to form the requireddoped areas within the substrate 1 together with the metallisation forthe required connections to the JFET and the sensing element of theMEMS. The process is therefore relatively inexpensive, and furthermoreis compatible with both n-type and p-type well designs. As previouslyindicated the parasitic leakage path from the edge of the gate of theJFET to the substrate can be reduced using a spacer 7 which can beformed without requiring an additional mask.

Alternatively such a parasitic leakage path may be eliminated using anannular transistor design which requires oxide isolation and contactholes, although this requires use of an additional mask to define thecontact holes. This will be described further below with reference toFIG. 4.

In a further optional step which may be added to the fabricationprocess, high resistance biasing resistors are formed by implantation atthe same time as the p-type well 5 is formed, windows for the resistorsbeing formed at the same time as the window 3 defining the well so thatno further masking step is required. Alternatively such resistors may bedefined by use of a further masking step prior to the first masking stepfor defining the p-type well 5 to define a resistor pattern in anadditional polysilicon layer deposited on the field oxide. This furthermasking step followed by selective etching enables windows to beproduced in the oxide layer through which a low dose dopant may beimplanted to form the resistors. In either case p⁺-type contact areasand metallisation tracks are required at the ends of the resistors soformed. In certain applications, this further step may form part of theMEMS process, being effected, for example, by polysilicon surfacemicromachining or in a thin metallic layer of suitable resistivity (ofTiN or TiW for example).

In SOI or SOG substrates, such resistors could also be formed by alength of silicon defined by etching channels in the silicon devicelayer down to the underlying insulating layer with dimensions to definethe required resistance R according to the relationship R=ρ1/hw, where ρis the resistivity of the silicon, l is the length of the resistor, h isits depth and w is its width. Highly doped regions may be formed viaimplantation for contacts as required. Substrate contacts in regionswith a JFET may limit the practical application of this approach.

The described fabrication processes can be used to readily fabricate aJFET which is integrated with a MEMS sensor. Typically the JFET isfabricated on the wafer prior to the application of deep reactive ionetching (DRIE) required to form the sensing element of the MEMS. If highaspect ratio machining (HARM) is used in a silicon-on-insulator (SOI) orsilicon on-glass (SOG) fabrication process, the process flow steps maybe as follows. The JFET is first fabricated using the sequence of stepsalready described up to immediately prior to the metallisation step. Themetallisation step follows, typically being common to both the JFET andthe MEMS production process. The MEMS structures are then defined usingdeep reactive ion etching (DRIE). As will more readily be appreciated byreferring to the description of a preferred MEMS sensor given withreference to the drawings of WO 00/16041, release etching (wet, vapourphase or plasma-based) may be necessary to free structures of the MEMSfrom the adjacent layer(s), and it may be necessary to protect theactive circuits during the release process since aluminium alloys (ifused) and/or silicon oxide (if used) are attacked by HF which may beused in such a process. The required protection may be provided by aprotection layer, such as a layer of photoresist, polyamide, PECVDsilicon nitride or other HF-resistant layer and combinations thereof.

In some applications, it may be preferable to define the metallisationafter the DRIE step to enable air bridges and/or dielectric or polymertrench refill to be employed (as described in copending PatentApplication No. 9819817.9) for mesa (or trench) isolation of individualJFET devices. This allows each JFET to have an independent substratevoltage and hence provides better matching of device characteristics incircuit implementations. In other applications more than onemetallisation step may be provided either before or after the DRIE andrelease step for added flexibility at the cost of increased processcomplexity. In alternative process flow sequences, the metallisationstep may be carried out as a final step, that is after release of theMEMS structures, using shadow masking and evaporation or sputtering (orsome other metal deposition technique, such as electroplating or CVD).Furthermore the JFET may be produced on top of a mesa in the silicon ifthis is of sufficient area. It should also be noted that DRIE may beused to form high value trench capacitors with appropriate refill. In afurther development of the invention described hereinbelow a bridgestructure across a trench is formed by DRIE.

To enable the JFET to be used for buffering applications, it may benecessary to incorporate a high resistivity polysilicon layer withinwhich resistors can be defined for biasing the JFET. This is estimatedto require one additional mask for edgeless device architectures and twoadditional masks for a simple spacer-based process. Using a diode tobias the JFET is an alternative choice that avoids the added complexityof additional processing steps and presents a large impedance as thediode is reverse biased when looking from the gate of the JFET. Thediode can be formed using the 4 mask layers outlined above. The diodewill be small and will be electrically connected to the gate of the JFETdevice. A low impedance voltage would be applied to the other end of thediode to establish the DC operating point of the JFET device. Theeffective resistance value of the diode will depend on the area of thediode and the magnitude of the voltage at the gate of the JFET.

As the skilled person will appreciate, the JFET could also be integratedwith a sacrificial surface micromachining process employing materialssuch as polysilicon, metal or metal-nitride for the mechanical layer.Typically the JFET would be fabricated in a step immediately prior tothe metallisation step and the metallisation would added as part of themain surface micromachining process flow. If this involves hightemperature (>700 C) processing steps, then the layout and anneal cyclesof the JFET process may need to be adjusted to allow for this. Sucheffects may be readily modelled using industry-standard process anddevice simulators obtainable from companies such as Silvaco, TMA,Avanti, Mentor and Cadence.

FIG. 3 shows a possible layout for the system in which source, gate anddrain metallisation electrodes 20, 21 and 22 overlie the p-type well 23in registry with the p⁺ contact area, the n⁺ gate contact area and thep⁺ drain contact area respectively so as to overlap the n-type siliconsubstrate 24, and a substrate contact metallisation electrode 25 isprovided in registry with the n⁺ substrate contact area so as to alsooverlap the substrate 24 surrounding the substrate contact area. Anenlarged detail of the part of the JFET denoted by the square overlay 26is shown at 27 from which it will be appreciated that the overlapbetween the electrode 21 and the p-type well 23 and the n-typesurrounding substrate 24 serves to form a parasitic n⁺-p-n edgetransistor connected to the gate of the JFET. Such a parasitic edgetransistor (bipolar) is undesirable in some applications as it may turnon before the JFET leading to high leakage currents.

FIG. 4 shows the layout of an alternative edgeless design in which asource metallisation electrode 30 surrounds a gate metallisationelectrode 31 which in turn surrounds a drain metallisation electrode 32,and the electrodes 30, 31 and 32 are in registry with correspondinglyshaped source, gate and drain contact areas formed within the p-typewell 33. Narrow metallisation tracks 35 and 36 extend through gaps inthe electrodes 30 and 31 in order to provide electrical connections tothe electrodes 31 and 32. Such an edgeless design substantiallyeliminates the parasitic edge transistor effect. However, in this case,a fifth mask is required to define contact holes 37 through aninsulating layer for interconnecting the electrodes 30, 31 and 32 andthe associated contact areas. Similarly such contact holes are providedfor connecting a substrate contact metallisation electrode 38 to theunderlying substrate contact area.

The further processing to produce this design requires deposition of alow temperature oxide (LTO) layer prior to metallisation and after thedry oxygen annealing step, and etching of contact holes through thislayer after patterning using the fifth mask and before deposition anddefinition of the metallisation. This LTO layer may be deposited byLPCVD (low pressure chemical vapour deposition) or PECVD (plasmaenhanced chemical vapour deposition) typically at a temperature below425° C. so that it may be deposited on top of an Al metallisationscheme, and serves to insulate the tracks 35 and 36 from the underlyingcontact areas. In this context low temperature means any process carriedout at temperatures under approximately 700° C., as temperatures above700° C. can cause diffusion of implants in the silicon at rates suchthat the device characteristics may be adversely affected, depending onthe temperature and the time of exposure. Thus the implant profile anddose, as well as the duration and temperatures of processes carried outabove these temperatures (such as thermal oxidation and anneals), needto be well known and reproducible in order to produce devices with thedesired characteristics. Typically the process is optimised by varyingthe implant anneal time. Such trends may be modelled using processsimulation software.

In a preferred implementation the JFET and associated fabricatedcomponents constitute a buffering circuit acting as an impedancetransformer which accordingly vastly reduces the parasitic effect of thebond wire connecting the MEMS sensing element to external detectioncircuitry, thus increasing the signal: noise ratio of the detectioncircuit as a whole. A source follower circuit may be used with one ormore associated active devices, capacitors and resistors. In itssimplest form, this source follower circuit requires only a single JFETin the circuit.

Two preferred circuit implementations are shown in FIGS. 5 and 6, andcorresponding schematic representations (not to scale) of the resultantcircuits implemented on silicon with a generic sensing element are shownin FIGS. 7 and 8. In each case the generic sensing element comprises anelectrode in the form of a movable mass 40 supported by a sprungsuspension 41 forming a sensing capacitor with a fixed electrode 42.Each of these circuits requires to be connected to four bond wires arerequired, that is two wires serving as the power rails for the circuit,one wire to provide the bias for the JFET and one wire to take theoutput signal off-chip.

In the first preferred embodiment shown in FIG. 5, a single JFET 50 isused as a source follower (with an associated biasing diode D_(Bias) andload resistor R₁) from a capacitive sensing element input. The source ofthe JFET is connected to V_(ss) (tpyically V_(SS)=0V in thisconfiguration) by the load transistor R₁, and the output is provided atthe junction between the source and the load resistor R₁. Furthermorethe substrate is connected to the gate as indicated by the broken lines51. In a variant, however, the substrate may be connected to the source.Such a circuit is advantageous in that it is a small footprint circuitand is therefore most suited to integration on an electrode of thesensing element itself. In this case the sensing electrode is anisolated mesa, as shown in FIG. 7.

The circuit layout of FIG. 7 is suitable for use in a 4 mm diameter ringgyroscope of the form disclosed in WO 00/16041 which incorporatessensing electrodes of an adequate footprint to include this circuit,having a surface area in excess of 105 μm². Such a circuit would only beused where necessary, for example for the sensing of secondary(rate-of-turn) signals close to the noise level present in the device.The layout incorporates four conductive bond pads, provided on an oxidelayer on a n-type silicon substrate 43, indicated by V_(Bias), V_(DD),V_(SS) and V_(out) for the attachment of bond wires connecting thecircuit to external circuitry. Furthermore the layout incorporates a p+source 44, a n+ gate 45 and a p+ drain 46 provided in a p-doped well 43Aof the JFET, as well as a n+ substrate contact 47, a biasing diode 48and a polysilicon or p-well load resistor 49, interconnected bymetallisation tracks as appropriate. A cross-section through such alayout is shown in FIG. 9, the interconnecting metallisation tracksbeing omitted for clarity. A metal air bridge 52 is shown spanning atrench 53 between two mesas.

In the second preferred embodiment shown in FIG. 6, two JFETs areemployed, that is a first JFET 60 serving as a source follower from acapacitive sensing input, and a second JFET 61 serving as a currentsource (active load) provided with two matched load resistors R₁ and R₂.The use of two closely matched JFETs 60, 61 in such an arrangementprovides improved performance and temperature tracking. In order to takefull advantage of the matching, the substrate contacts of the JFETs 60,61 should be independently settable, preferably by being isolated fromone another. To this end mesa isolation is employed with metal airbridges being provided between the mesas (and between the electrode andthe mesas) for interconnection of the two parts of the circuit, as shownin the layout of FIG. 8.

The source of the JFET 60 is connected to the drain of the JFET 61 bythe load transistor R₁, and the source of the JFET 61 is connected toground by the load resistor R₂ The gate of the JFET 61 is connected toV_(SS), and the output is provided at the junction between the loadresistor R₁ and the drain of the JFET 61. Furthermore the substrate isconnected to the source of each JFET 60, 61 as indicated by the brokenlines 62, 63.

The circuit layout of FIG. 8, which is again only employed in situationswhere it would be of significant benefit, incorporates four conductivebond pads, provided on an oxide layer on a n-type silicon substrate 63,indicated by V_(Bias), V_(DD), V_(SS) and V_(out) for the attachment ofbond wires. Furthermore the layout incorporates a p+ source 64, a n+gate 65 and a p+ drain 66 provided in a p-doped well 63A of the firstJFET, as well as a biasing diode 68 and a polysilicon or p-well loadresistor 69, interconnected by metallisation tracks as appropriate.However, in this embodiment, the layout also includes a p+ source 71, an+ gate 72 and a p+drain 73 of the second JFET, as well as an air bridge74 and a polysilicon or p-well load resistor 75, interconnected bymetallisation tracks such as 76. The air bridge permits electricalinterconnection of the two JFETs provided on two mesas isolated from oneanother by means of a trench in known manner. An additional implant anddiode isolation could be used to isolate the devices, but only at thecost of added process complexity.

In a further, non-illustrated embodiment, a differential amplifiercircuit provides a differential output dependent on signals receivedfrom two sensing electrodes provided on opposite sides of the ring of agyroscope. In this case the circuit comprises two JFETs connectedback-to-back (with associated biasing diodes and a common load (aresistive or an active JFET load) receiving inputs from respectivecapacitive sensing elements. The drain of each JFET is connected to thesupply rail by a respective resisistor, and the outputs are provided atthe junctions between the drains and the resistor.

Furthermore it is advantageous for certain MEMS devices to takeadvantage of the different properties of different crystal orientationsof silicon substrate. An example of these different properties is thefact that Young's modulus varies with radial angle in [100] siliconwhilst Young's modulus is isotropic in [111] silicon. An importantadvantage of use of a JFET is such an integrated device is that the JFETmay be monolithically integrated either on a [100] silicon substrate oron a [111] silicon substrate (using slightly different process detailsbut the same basic sequence of steps and masks). It is also believedthat other silicon substrate orientations, such as [110], could beaccommodated with only minor JFET process engineering, for example byvarying anneal and thermal oxidation times.

An example of a MEMS device in which such an arrangement is particularlyadvantageous is a ring gyroscope formed on a SOI or SOG substrate. Sucha device may be based on [111] silicon for which a JFET offers the mostviable solution for monolithic integration. It may also be preferable tomonolithically integrate only the bare minimum of circuitry with theMEMS before routing off-chip to the remainder of the electroniccircuitry, using either a bond wire or solder bump. The remainder of thecircuitry may be in the form of a dedicated ASIC fabricated in astand-alone CMOS process at minimum cost on standard [100] silicon. Thishelps to maximise the yield of the system as both the ASIC and theminimally integrated MEMS chip may be tested prior to assembly.

The electrodes of the MEMS sensing element may themselves besufficiently large to contain the associated buffering circuitry on topof them together with an associated bond pad for connection to anyoff-chip circuitry. Thus the total area of the MEMS die may not beeffected by the incorporation of the JFET circuitry.

In some applications, the JFET circuitry may require the substratesurface to be of a certain resistivity, typically 0.1-5000 ohm-cm andmore advantageously 10-20 ohm-cm, for optimal electronic performance.This may be in direct conflict with the MEMS requirement for the dopinglevel of the layer, for example a highly doped layer (less than 0.01ohm-cm) or a lightly doped layer (greater than 5000 ohm-cm). In thiscase it may be necessary to incorporate a layer at the appropriatedoping level on the surface of the wafer or at least in the activeregions. This may be achieved by using epitaxial growth, either inselected regions, or over the whole surface.

In a further development of the invention a novel approach is adoptedfor realising an interconnection track between two mesas as shown, forexample, in the circuit layouts of FIGS. 7 and 8 in such a manner as tosolve the problems inherent in forming metallisation between isolatedislands in high topography devices. In this approach the depositedmetallisation is patterned before the DRIE step to define the MEMSdevice to provide a narrow metal track between the two mesa areas. It isa feature of deep dry etching with a mask that the etching processslightly undercuts the mask prior to etching anisotropically down. Thus,provided that a suitably narrow interconnection track is provided, thesilicon underneath the track will be completely removed during the dryetching process. As a result the track will form a planar bridge 60across the continuous trench between the two mesas 61 and 62, as showndiagrammatically in FIG. 10, in spite of the track acting as a maskduring the etch. It should be noted that substantially no siliconremains beneath the bridge 60 after etching, and that the bridge 60 isin the plane of the metallisation on the two mesas.

Preferably the track is protected by a line of resist during theetching. Furthermore the arrangement is preferably such that the bridgeis short and the stress level in the bridge is slightly tensile to avoidbuckling. Typical ranges for the bridge width are 0.1-50 μm (preferablyapproximately 1 μm) and for bridge length are 1-200 μm (preferably 2-20μm). One potential advantage of such a bridge structure is that thebridge is less sensitive to stress as the bridge structure will remainessentially planar (if the layer is tensile).

This novel approach has advantages over a process in which a metal trackis patterned over a silicon bridge and then the bridge removed bypost-processing (e.g. using XeF₂) as it saves additional process stepsand does not compromise gap sizes in capacitive structures formed in themain silicon etch step for sensing and actuation (e.g. comb drives andparallel plate capacitors).

A wet release process is typically employed (HF-based), in which casethe metallisation must be HF resistant. Thus TiW and/or TiN arepreferred adhesion/barrier layers with Pt and/or Au being used for anupper metallisation layer. Cr is a possible alternative adhesion/barrierlayer. The barrier layer may be attacked slightly during deep dryetching in the portions being undercut, so that it is preferable toprovide an upper metallisation layer. Where the substrate ispre-cavitated, no such HF-resistance is required and hence Al-basedmetallisations may similarly be employed.

This development is not limited to silicon-on-insulator (SOI) devicesbut is equally applicable to silicon-on-glass (SOG) andsilicon-on-sapphire (SOS) devices, as well as being applicable to bulksilicon devices where etched mesas are isolated by diode isolation, etc.Furthermore, although the above discussion is concerned with laterallyundercutting the metal track to form a bridge in a DRIE process, it isalso possible to utilise such an approach to provide a limited degree ofundercut, for example to use wet anisotropic etching to define a silicondevice.

If desired, an HF-resistant insulating layer, made for example ofsilicon nitride rather than the previously discussed silicon oxide, maybe employed prior to metallisation to permit tracking on a silicon mesa,such as in a SOI MEMS process with integrated JFETs. This would requirethe previously described additional lithography level to permit contactwindows to be defined to the silicon prior to metal deposition.

Such a process of undercutting a patterned structure on a surface toform a planar bridge structure using DRIE may be also be used in otherapplications. For example such a process may be used to form a series ofcantilevers anchored on one side of a gap but not on the other so as tomechanically constrain the unattached end.

Such cantilevers may be fabricated in conductive materials (e.g.metals), semiconducting materials (e.g. polysilicon) or insulatingmaterials (e.g. silicon nitride) according to application requirements.

1. A method of fabricating a micro-electromechanical system (MEMS)incorporating a sensing element and a junction field-effect transistor(JFET) electrically connected to the sensing element, the methodcomprising the steps of: (a) forming a first layer of electricallyinsulating barrier material on a surface of a substrate; (b) patterningthe first layer so as to expose a first region of the substrate; (c)doping by ion implantation the first region of the substrate to form awell region of the JFET; (d) forming a second layer of barrier materialon the surface of both the first layer and the first region of thesubstrate; (e) patterning the barrier material so as to expose a part ofthe first region of the substrate; (f) doping by ion implantation theexposed part of the first region of the substrate to form source anddrain contact areas of the JFET; (g) patterning the barrier material soas to expose a second region of the substrate; and (h) doping by ionimplantation the second region of the substrate to form gate andsubstrate contact areas of the JFET in a single implantation step.
 2. Amethod according to claim 1, wherein, prior to patterning of the secondlayer in step (e), the thickness of the second layer on the substrate issubstantially less than the combined thickness of the first and secondlayers where these are superimposed on the substrate, so that sufficientbarrier material remains to prevent ion implantation in the secondregion in step (f).
 3. A method according to claim 1, wherein, in afurther step to reduce gate-to-substrate leakage, a spacer is formedaround the edge of a well formed by coating of the first region with thesecond layer.
 4. A method according to claim 3, wherein the spacer isformed by forming another layer of barrier material on the second layerand by directionally etching said other layer over the whole of itsextent to leave the spacer in the areas where the layer is thicker dueto the underlying topology.
 5. A method according to claim 1, wherein,during patterning of the barrier material so as to expose said part ofthe first region through which the source and drain contact areas areimplanted, portions of the barrier layer are etched to expose said partand simultaneously further portions of the layer overlying the secondregion are etched only part of the way through the thickness of thelayer.
 6. A method according to any claim 1, wherein an annealing stepis provided for activating the doping.
 7. A method according to claim 1,wherein a metallisation step is provided in which one or moremetallisation layers are deposited and patterned to form electricallyconductive connections to the contact areas of the JFET and the sensingelement.
 8. A method according to claim 7, wherein a further patterningstep is provided in which contact holes are formed in a further layer ofbarrier material for establishing electrical contact between theelectrical conductive connections and the contact areas.
 9. A methodaccording to claim 1, wherein a resistor forming step is provided inwhich at least one biasing resistor is formed by depositing andpatterning a further layer of material and doping an area exposed suchpatterning to form the biasing resistor—not in substrate typically inadditional polysilicon layer on the oxide.
 10. A method according toclaim 9, wherein the further layer of material is a polysilicon layer.11. A method according to claim 1, wherein a biasing diode junction forbiasing the JFET is formed by the fabrication steps.
 12. A methodaccording to claim 1, wherein each patterning step involves alithographic process in which the layer is selectively exposed through aphotoresist mask and the layer is selectively etched.
 13. A methodaccording to claim 1, wherein an epitaxial layer is formed at least inselected regions on the surface of the substrate.
 14. A method accordingto claim 1, wherein a mechanical actuator of the MEMS is formed by deepreactive ion etching (DRIE), by anisotropic wet etching or bysacrificial surface micromachining.
 15. A micro-electromechanical system(MEMS) comprising a substrate incorporating a movable element and anelectrical sensing element providing an electrical output signalindicative of actuation of the movable element, wherein a junctionfield-effect transistor (JFET) is monolithically integrated on thesubstrate with the sensing element and is electrically connected to thesensing element so as to act as an impedance transformer rendering theoutput signal less sensitive to external effects, and wherein gate andsubstrate contact areas of the JFET are formed on the same side of thesubstrate by a single ion implantation step.
 16. A system according toclaim 15, wherein the sensing element is a capacitive element which iscapacitatively coupled to the actuator to an extent dependent on motionof the actuator.
 17. A micro-electromechanical system (MEMS) comprisinga substrate incorporating a sensing element and a junction field-effecttransistor (JFET) electrically connected to the sensing element, thesystem being formed by a method according to claim
 1. 18. A systemaccording to claim 15, wherein the JFET is formed in the sensingelement.
 19. A system according to claim 15, wherein the JFET is definedby a well, and a spacer is formed around the edge of the well.
 20. Asystem according to claim 15, wherein the substrate incorporates twocircuit parts separated by mesa isolation to permit different substratepotentials in the two circuit parts.
 21. A system according to claim 20,wherein the two circuit parts are interconnected by means of one or moreair bridges or isolation refill bridges.
 22. A system according to claim15, wherein connections to contacts of the JFET are formed throughcontact holes in an insulating layer so as to substantially avoid theproduction of parasitic edge transistors.
 23. A system according toclaim 15, wherein the layer in which the JFET is formed in crystallinen-type silicon.
 24. A system according to claim 15, wherein the layer inwhich the JFET is formed in crystalline p-type silicon.
 25. A systemaccording to claim 15, wherein the JFET is formed in an epitaxial layeron the substrate of a different doping level to an underlying substratelayer.
 26. A system according to claim 25, wherein the JFET is formed inan epitaxial layer on the substrate and the movable element is formed inan adjacent portion of the substrate in which the epitaxial layer is notpresent.
 27. A system according to claim 15, wherein the substrate is aSOI, SOG or SOS substrate.
 28. A method of fabricating amicro-electromechanical system (MEMS), the method comprising the stepsof applying a layer of a first material on a surface of a substrate of asecond material, selectively patterning the first material so as to forma track extending between two areas of the surface, and deep etching thesecond material so as to form a trench between the two areas whilstleaving the patterned first material in place, the deep etching beingadapted to undercut the second material beneath the track so that thetrack forms a bridge or cantilever across the trench.
 29. A methodaccording to claim 28, wherein the first material is a metal and thesecond material is silicon.
 30. A method according to claim 28, whereinthe bridge forms a planar structure providing an interconnection betweentwo circuit areas.